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Re: Serial D-1 Jitter
>Chyron solved the problem by lending us a reclocking DA and
>pretending that they will fix it sometime!!! Some Fix!!
Its been my experience that "reclocking" DAs just reshape the jitter, in
essence just passing along a cleaned up version with nearly equal jitter.
There must be a better way (like maybe better phase lock loop design ;-) Is
anyone aware of reclocking DAs that really do eliminate jitter?
On the Rank output side of things, I just did Rank change note 33102 that
provides a more direct route for 27 Mhz between the 1030 and 934 board, and
it has helped clean up the eye pattern a little in Pal, but it is far from
The other changes they are suggesting is hand picking some of the ICs. I
have not tried this somewhat "voodotronic" approach yet, but Rank has a list
of "the usual suspects".
I know that Mark IIIs and Ursas suffer from about the same jitter. The Gold
uses a little different sync generator scheme to generate the clock. Is it
any more stable?